NXP Semiconductors MKW01Z128, Reference Manual, Page: 164 / 884

Table 1-4. ARM Cortex-M0+ parameter settings (continued)
Parameter Verilog name Value Description
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM table
Endianess BE 0 Little endian control for data transfers
Breakpoints BKPT 2 Implements 2 breakpoints
Debug Support DBG 1 = Present —
Halt Event Support HALTEV 1 = Present —
I/O Port IOP 1 = Present Implements single-cycle ld/st accesses to
special address space
IRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs are used (set if
IRQ is disabled)
Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAG
Core Memory Protection MPU 0 = Absent No MPU
Number of IRQs NUMIRQ 32 Assume full NVIC request vector
Reset all registers RAR 0 = Standard Do not force all registers to be async reset
Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier
Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multi-
drop
System Tick Timer SYST 1 = Present Implements system tick timer (for CM4
compatibility)
DAP Target ID TARGETID 0 —
User/Privileged USER 1 = Present Implements processor operating modes
Vector Table Offset Register VTOR 1 = Present Implements relocation of exception vector
table
WIC Support WIC 1 = Present Implements WIC interface
WIC Requests WICLINES 34 Exact number of wake-up IRQs is 34
Watchpoints WPT 2 Implements two watchpoints
For details on the ARM Cortex-M0+ processor core, see the ARM website:
arm.com
.
1.3.1.2 Buses, interconnects, and interfaces
The ARM Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 33