NXP Semiconductors MKW01Z128, Reference Manual

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4.2.3.6 Chip Reset
Chip Reset asserts on all reset sources and only negates after flash initialization has
completed and the RESET pin has also negated. It resets the remaining modules (the
modules not reset by other reset types).
4.2.4 RESET pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the
RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash
initialization has completed.
After flash initialization has completed, the RESET pin is released, and the internal Chip
Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted
externally delays the negation of the internal Chip Reset.
The RESET pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG]
option bit to 0 (See
Table 4-2 ). When this option is selected, there could be a short period
of contention during a POR ramp where the device drives the pinout low prior to
establishing the setting of this option and releasing the reset function on the pin.
4.2.5 Debug resets
The following sections detail the debug resets available on the device.
4.2.5.1 Resetting the Debug subsystem
Use the CDBGRSTREQ field within the DP CTRL/STAT register to reset the debug
modules. However, as explained below, using the CDBGRSTREQ field does not reset all
debug-related registers.
CDBGRSTREQ resets the debug-related registers within the following modules:
• SW-DP
• AHB-AP
• MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• BPU
Chapter 4 Reset and Boot
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 109