NXP Semiconductors MKW01Z128, Reference Manual

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data from a source memory location to a destination memory location with the module
operating as a 32-bit bus master connected to the system bus. The programming model is
accessed through a 32-bit connection with the slave peripheral bus. DMA data transfers
may be explicitly initiated by software or by peripheral hardware requests.
The following figure is a simplified block diagram of the 4-channel DMA controller.
SAR0
DAR0
DSR0
BCR0
DCR0
Channel 0
SAR1
DAR1
DSR1
BCR1
DCR1
Channel 1
SAR2
DAR2
DSR2
BCR2
DCR2
Channel 2
SAR3
DAR3
DSR3
BCR3
DCR3
Channel 3
DREQ2
DACK3
DREQ0 DREQ1
Data Path
DREQ3
Addr + Attr
Interrupts
Phase Bus Signals
Current Master Attributes
Write Data Bus Read Data Bus
System Bus Address
System Bus Size
SysBus Interface
MUX
SysBus Interface
Registered Addr
DACK2
DACK1
DACK0
Slave
Peripheral Bus
Channel
Requests
Channel
Enables
Channel
Attributes
MUX
Control
Arbitraton/
Control
Data Path
Control
Figure 19-1. 4-Channel DMA Block Diagram
The terms peripheral request and DREQ refer to a DMA request from one of the on-chip
peripherals or package pins. The DMA provides hardware handshake signals: either a
DMA acknowledge (DACK) or a done indicator back to the peripheral.
19.1.2 Features
The DMA controller module features:
• Four independently programmable DMA controller channels
Introduction
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
318 Freescale Semiconductor, Inc.