NXP Semiconductors MKW01Z128, Reference Manual

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The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode,
the maximum rate at which the CNR can increment is once every 2
2
to 2
16
prescaler
clock edges. When first enabled, the glitch filter will wait an additional one or two
prescaler clock edges due to synchronization logic.
29.4.3.4 Glitch filter bypassed
In Pulse Counter mode, when the glitch filter is bypassed, the selected input source
increments the CNR every time it asserts. Before the LPTMR is first enabled, the selected
input source is forced to be asserted. This prevents the CNR from incrementing if the
selected input source is already asserted when the LPTMR is first enabled.
29.4.4 LPTMR compare
When the CNR equals the value of the CMR and increments, the following events occur:
• CSR[TCF] is set.
• LPTMR interrupt is generated if CSR[TIE] is also set.
• LPTMR hardware trigger is generated.
• CNR is reset if CSR[TFC] is clear.
When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. When
updating the CMR, the CMR must be written and CSR[TCF] must be cleared before the
LPTMR counter has incremented past the new LPTMR compare value.
29.4.5 LPTMR counter
The CNR increments by one on every:
• Prescaler clock in Time Counter mode with prescaler bypassed
• Prescaler output in Time Counter mode with prescaler enabled
• Input source assertion in Pulse Counter mode with glitch filter bypassed
• Glitch filter output in Pulse Counter mode with glitch filter enabled
The CNR is reset when the LPTMR is disabled or if the counter register overflows. If
CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set.
The CNR continues incrementing when the core is halted in Debug mode when
configured for Pulse Counter mode, the CNR will stop incrementing when the core is
halted in Debug mode when configured for Time Counter mode.
Chapter 29 Low-Power Timer (LPTMR)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 561