NXP Semiconductors MKW01Z128, Reference Manual, Page: 181 / 884

WDOG
Mode C
ontr
oller
Peripheral
bridge 0
Register
access
Figure 1-13. COP watchdog configuration
Table 1-22. Reference links to related information
Topic Related module Reference
Clocking — Clock distribution
Power management — Power management
Programming model System integration
module (SIM)
SIM
1.4.10.1 COP clocks
The multiple clock inputs for the COP are:
• 1 kHz clock
• bus clock
1.4.10.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails
to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), the application software must reset the COP counter periodically. If the
application program gets lost and fails to reset the COP counter before it times out, a
system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an
application, it can be disabled by clearing SIM_COPC[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the
SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not
affect the data in the SRVCOP register. As soon as the write sequence is complete, the
COP timeout period is restarted. If the program fails to perform this restart during the
timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is
written to the SRVCOP register, the microcontroller immediately resets.
System modules
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
50 Freescale Semiconductor, Inc.