NXP Semiconductors MKW01Z128, Reference Manual

Page: 754 / 884

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h 32.2.9/633
4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h
32.2.10/
634
4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 0Fh
32.2.11/
634
4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h
32.2.12/
635
32.2.1 UART Baud Rate Register High (UARTx_BDH)
This register, along with UART_BDL, controls the prescale divisor for UART baud rate
generation. The 13-bit baud rate setting [SBR12:SBR0] should only be updated when the
transmitter and receiver are both disabled.
Address: Base a 0h offset
Bit 7 6 5 4 3 2 1 0
Read
LBKDIE RXEDGIE SBNS SBR
Write
Reset 0 0 0 0 0 0 0 0
UARTx_BDH field descriptions
Field Description
7
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
6
RXEDGIE
RX Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
5
SBNS
Stop Bit Number Select
SBNS determines whether data characters are one or two stop bits. This bit should only be changed when
the transmitter and receiver are both disabled.
0 One stop bit.
1 Two stop bit.
SBR Baud Rate Modulo Divisor.
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the
baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR).
Chapter 32 Universal asynchronous receiver/transmitter (UART0)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 623