NXP Semiconductors MKW01Z128, Reference Manual

Page: 60 / 884

Sub 1 GHz Transceiver Architecture Description
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 5-5
automatically starts the receiver or the transmitter when the PLL has locked. To manually control the
startup time, the user should either wait for
TS_FS max given in the specification, or monitor the signal
PLL lock detect indicator, which is set when the PLL has is within its locking range.
When performing an AFC, which usually corrects very small frequency errors, the PLL response time is
approximately:
In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of
magnitude for the expected lock times.
5.5.5 Lock Detect Indicator
A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL
reaches its locking range. Refer to
Table 7-2 and Table 7-3 to map this interrupt to the desired pins.
NOTE
The lock detect block may indicate an unlock condition (signal toggling
low) when the transmitter is FSK modulated with large frequency deviation
settings.
5.6 Transmitter Description
The transmitter of MKW01Z128 transceiver is comprised of the frequency synthesizer, modulator and
power amplifier blocks.
Figure 5-3. Transmitter Block Diagram
T
PLLAFC
5
PLLBW
--------------------- =
PLLBW default = Varies by region; see Table 7-11 for settings.
LNA
Receiver Chain RFIO
Local
Oscillator
PA0
PA1
PA2
PA_BOOST