NXP Semiconductors MKW01Z128, Reference Manual, Page: 774 / 884

32.3.4.2 Loop mode
When UART_C1[LOOPS] is set, the UART_C1[RSRC] bit in the same register chooses
between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] =
1). Loop mode is sometimes used to check software, independent of connections in the
external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the UART_RX pin is not used by the
UART.
32.3.4.3 Single-wire operation
When UART_C1[LOOPS] is set, the RSRC bit in the same register chooses between
loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1).
Single-wire mode implements a half-duplex serial connection. The receiver is internally
connected to the transmitter output and to the UART_TX pin (the UART_RX pin is not
used).
In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on
the UART_TX pin. When UART_C3[TXDIR] is cleared, the UART_TX pin is an input
to the UART receiver and the transmitter is temporarily disconnected from the
UART_TX pin so an external device can send serial data to the receiver. When
UART_C3[TXDIR] is set, the UART_TXD pin is an output driven by the transmitter, the
internal loop back connection is disabled, and as a result the receiver cannot receive
characters that are sent out by the transmitter.
32.3.5 Interrupts and status flags
The UART system generates three separate interrupts to reduce the amount of software
needed to isolate the cause of the interrupt.
One interrupt is associated with the transmitter for TDRE and TC events. Another
interrupt is associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF
events. A third interrupt is used for OR, NF, FE, and PF error conditions. Each of these
ten interrupt sources can be separately masked by local interrupt enable masks. The flags
can be polled by software when the local masks are cleared to disable generation of
hardware interrupt requests.
The UART transmitter has two status flags that can optionally generate hardware
interrupt requests. Transmit data register empty (UART_S1[TDRE]) indicates when there
is room in the transmit data buffer to write another transmit character to UART_D. If the
transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested
when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the
Chapter 32 Universal asynchronous receiver/transmitter (UART0)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 643