NXP Semiconductors MKW01Z128, Reference Manual, Page: 252 / 884

Table 5-2. Module operation in low power modes (continued)
Modules VLPR VLPW Stop VLPS LLS VLLSx
static in CPO FF in PSTOP2
Clocks
1kHz LPO ON ON ON ON ON ON in VLLS1/3,
OFF in VLLS0
System
oscillator (OSC) OSCERCLK
max of 16MHz
crystal
OSCERCLK
max of 16MHz
crystal
OSCERCLK
optional
OSCERCLK
max of 16MHz
crystal
limited to low
range/low power
limited to low
range/low power
in VLLS1/3, OFF
in VLLS0
MCG 4 MHz IRC 4 MHz IRC static -
MCGIRCLK
optional; PLL
optional
static -
MCGIRCLK
optional
static - no clock
output
OFF
Core clock 4 MHz max OFF OFF OFF OFF OFF
Platform clock 4 MHz max 4 MHz max OFF OFF OFF OFF
System clock 4 MHz max
OFF in CPO
4 MHz max OFF OFF OFF OFF
Bus clock 1 MHz max
OFF in CPO
1 MHz max OFF
24 MHz max in
PSTOP2 from
RUN
1 MHz max in
PSTOP2 from
VLPR
OFF OFF OFF
Memory and memory interfaces
Flash 1 MHz max
access - no
program
No register
access in CPO
low power low power low power OFF OFF
SRAM_U and
SRAM_L low power low power low power low power low power low power in
VLLS3, OFF in
VLLS0/1
System Register
File powered powered powered powered powered powered
Communication interfaces
UART0 1 Mbit/s
Async operation
in CPO
1 Mbit/s Async operation
FF in PSTOP2
Async operation static OFF
UART1 , UART2 62.5 kbit/s
static, wakeup
on edge in CPO
62.5 kbit/s static, wakeup
on edge
FF in PSTOP2
static, wakeup
on edge
static OFF
SPI0 master mode
500 kbit/s,
slave mode 250
kbit/s
master mode
500 kbit/s,
slave mode 250
kbit/s
static, slave
mode receive
FF in PSTOP2
static, slave
mode receive
static OFF
Table continues on the next page...
Chapter 5 Power Management
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 121