NXP Semiconductors MKW01Z128, Reference Manual

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6.5 Micro Trace Buffer (MTB)
The Micro Trace Buffer (MTB) provides a simple execution trace capability for the
Cortex-M0+ processor.
When enabled, the MTB records changes in program flow reported by the Cortex-M0+
processor, via the execution trace interface, into a configurable region of the SRAM.
Subsequently, an off-chip debugger may extract the trace information, which would
allow reconstruction of an instruction flow trace. The MTB does not include any form of
load/store data trace capability or tracing of any other information.
In addition to providing the trace capability, the MTB also operates as a simple AHB-Lite
SRAM controller. The system bus masters, including the processor, have read/write
access to all of the SRAM via the AHB-Lite interface, allowing the memory to be also
used to store program and data information. The MTB simultaneously stores the trace
information into an attached SRAM and allows bus masters to access the memory. The
MTB ensures that trace information write accesses to the SRAM take priority over
accesses from the AHB-Lite interface.
The MTB includes trace control registers for configuring and triggering the MTB
functions. The MTB also supports triggering via TSTART and TSTOP control functions
in the MTB DWT module.
6.6 Debug in low-power modes
In low-power modes, in which the debug modules are kept static or powered off, the
debugger cannot gather any debug data for the duration of the low-power mode.
• In the case that the debugger is held static, the debug port returns to full functionality
as soon as the low-power mode exits and the system returns to a state with active
debug.
• In the case that the debugger logic is powered off, the debugger is reset on recovery
and must be reconfigured once the low-power mode is exited.
Power mode entry logic monitors Debug Power Up and System Power Up signals from
the debug port as indications that a debugger is active. These signals can be changed in
RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to
enter Stop or VLPS, FCLK continues to run to support core register access. In these
modes in which FCLK is left active the debug modules have access to core registers but
not to system memory resources accessed via the crossbar.
Chapter 6 Debug
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 131