NXP Semiconductors MKW01Z128, Reference Manual

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UARTx_C2 field descriptions (continued)
Field Description
0 Hardware interrupts from S1[IDLE] disabled; use polling.
1 Hardware interrupt requested when S1[IDLE] flag is 1.
3
TE
Transmitter Enable
TE must be 1 to use the UART transmitter. When TE is set, the UART forces the TxD pin to act as an
output for the UART system.
When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the
direction of traffic on the single UART communication line (TxD pin).
TE can also queue an idle character by clearing TE and then setting TE while a transmission is in
progress.
When 0 is written to TE, the transmitter keeps control of the port TxD pin until any data, queued idle, or
queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
0 Transmitter off.
1 Transmitter on.
2
RE
Receiver Enable
When the UART receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If C1[LOOPS]
is set, the RxD pin reverts to being a general-purpose I/O pin even if RE is set.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control
A 1 can be written to this field to place the UART receiver in a standby state where it waits for automatic
hardware detection of a selected wake-up condition. The wake-up condition is an idle line between
messages, WAKE = 0, idle-line wake-up, or a logic 1 in the most significant data bit in a character, WAKE
= 1, address-mark wake-up. Application software sets RWU and, normally, a selected hardware condition
automatically clears RWU.
0 Normal UART receiver operation.
1 UART receiver in standby waiting for wake-up condition.
0
SBK
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 or 12, 13 or 14 or 15 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is
set. Depending on the timing of the set and clear of SBK relative to the information currently being
transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 653