NXP Semiconductors MKW01Z128, Reference Manual, Page: 293 / 884

SIM_SCGC4 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
5–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
8.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PORTE PORTD PORTC PORTB PORTA
1 0
TSI
0 1
LPTMR
W
Reset
0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0
SIM_SCGC5 field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
PORTE
Port E Clock Gate Control
Controls the clock gate to the Port E module.
Table continues on the next page...
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
162 Freescale Semiconductor, Inc.