NXP Semiconductors MKW01Z128, Reference Manual, Page: 205 / 884

1.9 Communication interfaces
1.9.1 SPI configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Register
access
SPI
Peripheral
bridge
Module signals
Figure 1-29. SPI configuration
Table 1-44. Reference links to related information
Topic Related module Reference
Full description SPI SPI
System memory map — System memory map
Clocking — Clock distribution
Signal multiplexing Port control Signal multiplexing
1.9.1.1 SPI instantiation information
This device contains two SPI module that supports 16-bit data length.
SPI1 includes a 4-deep FIFO.
SPI0 is clocked on the bus clock. SPI1 is clocked from the system clock. SPI1 is
therefore disabled in "Partial Stop Mode".
The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave.
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode.
Communication interfaces
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
74 Freescale Semiconductor, Inc.