NXP Semiconductors MKW01Z128, Reference Manual

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1.5.1.1 MCG FLL modes
The MCGFLLCLK frequency is limited to 48 MHz at maximum in this device. The
digitally-controller oscillator (DCO) is limited to the two lowest range settings, that is,
MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01.
1.5.2 OSC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal m
ultiple
xing
Register
access
Peripheral
bridge
System oscillator
MCG
Module signals
R
TC
Figure 1-15. OSC configuration
Table 1-25. Reference links to related information
Topic Related module Reference
Full description OSC OSC
System memory map — System memory map
Clocking — Clock distribution
Power management — Power management
Signal multiplexing Port control Signal multiplexing
Full description MCG MCG
1.5.2.1 OSC modes of operation with MCG and RTC
The most common method of controlling the OSC block is through MCG_C1[CLKS] and
the fields of MCG_C2 register to configure the oscillator frequency range, gain-mode,
and for crystal or external clock operation. OSC_CR also provides control for enabling
the OSC module and configuring internal load capacitors for the EXTAL and XTAL
pins. See the
OSC and MCG chapters for more details.
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 53