NXP Semiconductors MKW01Z128, Reference Manual

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PORTx_PCRn field descriptions (continued)
Field Description
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
IRQC
Interrupt Configuration
This field is read-only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:
0000 Interrupt Status Flag (ISF) is disabled.
0001 ISF flag and DMA request on rising edge.
0010 ISF flag and DMA request on falling edge.
0011 ISF flag and DMA request on either edge.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 ISF flag and Interrupt when logic 0.
1001 ISF flag and Interrupt on rising-edge.
1010 ISF flag and Interrupt on falling-edge.
1011 ISF flag and Interrupt on either edge.
1100 ISF flag and Interrupt when logic 1.
1101 Reserved.
1110 Reserved.
1111 Reserved.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
MUX Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (Alternative 0) (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
142 Freescale Semiconductor, Inc.