NXP Semiconductors MKW01Z128, Reference Manual, Page: 310 / 884

SMC_PMPROT field descriptions (continued)
Field Description
0 VLPR, VLPW, and VLPS are not allowed.
1 VLPR, VLPW, and VLPS are allowed.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
ALLS
Allow Low-Leakage Stop Mode
Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter
any low-leakage stop mode (LLS).
0 LLS is not allowed
1 LLS is allowed
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
AVLLS
Allow Very-Low-Leakage Stop Mode
Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter
any very-low-leakage stop mode (VLLSx).
0 Any VLLSx mode is not allowed
1 Any VLLSx mode is allowed
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9.3.2 Power Mode Control register (SMC_PMCTRL)
The PMCTRL register controls entry into low-power Run and Stop modes, provided that
the selected power mode is allowed via an appropriate setting of the protection
(PMPROT) register.
NOTE
This register is reset on Chip POR not VLLS and by reset types
that trigger Chip POR not VLLS. It is unaffected by reset types
that do not trigger Chip POR not VLLS. See the Reset section
details for more information.
Address: 4007_E000h base + 1h offset = 4007_E001h
Bit 7 6 5 4 3 2 1 0
Read
Reserved RUNM
0 STOPA
STOPM
Write
Reset 0 0 0 0 0 0 0 0
Chapter 9 System Mode Controller (SMC)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 179