NXP Semiconductors MKW01Z128, Reference Manual

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Chapter 19
DMA Controller Module
19.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
Information found here describes the direct memory access (DMA) controller module. It
provides an overview of the module and describes in detail its signals and programming
model.
The latter sections of this chapter describe operations, features, and supported data
transfer modes in detail.
An example of using several features of the DMA module is described in AN4631: Using
the Asynchronous DMA features of the Kinetis L Series .
Note
The designation n is used throughout this section to refer to
registers or signals associated with one of the four identical
DMA channels: DMA0, DMA1, DMA2, or DMA3.
19.1.1 Overview
The DMA controller module enables fast transfers of data, providing an efficient way to
move blocks of data with minimal processor interaction. The DMA module, shown in the
following figure, has four channels that allow 8-bit, 16-bit, or 32-bit data transfers. Each
channel has a dedicated Source Address register (SARn), Destination Address register
(DARn), Status register (DSRn), Byte Count register (BCRn), and Control register
(DCRn). Collectively, the combined program-visible registers associated with each
channel define a transfer control descriptor (TCD). All transfers are dual address, moving
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 317