NXP Semiconductors MKW01Z128, Reference Manual, Page: 747 / 884

SPIx_C2 = 0xC0(%11000000)
Bit 3 BIDIROE = 0 SPI data I/O pin acts as input
Bit 2 RXDMAE = 0 DMA request disabled
Bit 1 SPISWAI = 0 SPI clocks operate in wait mode
Bit 0 SPC0 = 0 uses separate pins for data input and output
SPIx_BR = 0x00(%00000000)
Bit 7 = 0 Reserved
Bit 6:4 = 000 Sets prescale divisor to 1
Bit 3:0 = 0000 Sets baud rate divisor to 2
SPIx_S = 0x00(%00000000)
Bit 7 SPRF = 0 Flag is set when receive data buffer is full
Bit 6 SPMF = 0 Flag is set when SPIx_MH/ML = receive data buffer
Bit 5 SPTEF = 0 Flag is set when transmit data buffer is empty
Bit 4 MODF = 0 Mode fault flag for master mode
Bit 3:0 = 0 FIFOMODE is not enabled
SPIx_MH = 0xXX
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register
will be ignored.
SPIx_ML = 0xXX
Holds bits 0–7 of the hardware match buffer.
SPIx_DH = 0xxx
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by
the receive buffer.
SPIx_DL = 0xxx
Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
Initialization/application information
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
616 Freescale Semiconductor, Inc.