NXP Semiconductors MKW01Z128, Reference Manual, Page: 653 / 884

Table 27-2. Mode, Edge, and Level Selection (continued)
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
01 Low-true pulses (set
Output on match-up,
clear Output on match-
down)
Address: Base a Ch (8d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 CHF
CHIE MSB MSA ELSB ELSA
0
DMA
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_CnSC field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
CHF
Channel Flag
Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit.
Writing a 0 to CHF has no effect.
If another event occurs between the CHF sets and the write operation, the write operation has no effect;
therefore, CHF remains set indicating another event has occurred. In this case a CHF interrupt request is
not lost due to the delay in clearing the previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
6
CHIE
Channel Interrupt Enable
Enables channel interrupts.
0 Disable channel interrupts.
1 Enable channel interrupts.
5
MSB
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When
a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
4
MSA
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When
a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
3
ELSB
Edge or Level Select
Table continues on the next page...
Memory Map and Register Definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
522 Freescale Semiconductor, Inc.