NXP Semiconductors MKW01Z128, Reference Manual

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For a 9-bit data or 2 stop bits character, data sampling of the stop bit takes the receiver 10
bit times x 16 RT 10 RT cycles = 170 RT cycles.
With the misaligned character shown in, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit or 2 stop bits character with no errors is:
((170 - 176) / 170) x 100 = 3.53%
For a 9-bit data and 2 stop bits character, data sampling of the stop bit takes the receiver
11 bit times x 16 RT 10 RT cycles = 186 RT cycles.
With the misaligned character shown in, the receiver counts 186 RT cycles at the point
when the count of the transmitting device is 12 bit times x 16 RT cycles = 192 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit and 2 stop bits character with no errors is:
((186 - 192) / 186) x 100 = 3.23%
33.4.6 DMA Operation
In the transmitter, flags TDRE and TC can be configured to assert a DMA transfer
request. In the receiver, flags RDRF, IDLE and LBKDIF can be configured to assert a
DMA transfer request.
The table found here shows the configuration bit settings required to configure each flag
for DMA operation.
Table 33-4. DMA configuration
Flag Request enable bit DMA select bit
TDRE TIE = 1 TDMAS = 1
TC TCIE = 1 TCDMAS = 1
RDRF RIE = 1 RDMAS = 1
IDLE ILIE = 1 ILDMAS = 1
LBKDIF LBKDIE = 1 LBKDDMAS = 1
When a flag is configured for a DMA request, its associated DMA request is asserted
when the flag is set. When the RDRF or IDLE flag is configured as a DMA request, the
clearing mechanism of reading UART_S1 followed by reading UART_D does not clear
the associated flag.The DMA request remains asserted until an indication is received that
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 669