NXP Semiconductors MKW01Z128, Reference Manual

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• If entering FBE, clear C1[IREFS] to switch to the external reference and change
C1[CLKS] to 2'b10 so that the external reference clock is selected as the system
clock source. The C1[FRDIV] bits should also be set appropriately here
according to the external reference frequency to keep the FLL reference clock in
the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still
on in FBE mode.
• The internal reference can optionally be kept running by setting C1[IRCLKEN].
This is useful if the application will switch back and forth between internal and
external modes. For minimum power consumption, leave the internal reference
disabled while in an external clock mode.
3. Once the proper configuration bits have been set, wait for the affected bits in the
MCG status register to be changed appropriately, reflecting that the MCG has moved
into the proper mode.
• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] was
also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that
the external clock source has finished its initialization cycles and stabilized.
• If in FEE mode, check to make sure S[IREFST] is cleared before moving on.
• If in FBE mode, check to make sure S[IREFST] is cleared and S[CLKST] bits
have changed to 2'b10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed, it is still on in FBE mode.
4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency
range.
• By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO
output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280
is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency
of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the
C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high-
range FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to
2'b11 for a DCO output frequency of 80 MHz.
• When using a 32.768 kHz external reference, if the maximum low-range DCO
frequency that can be achieved with a 32.768 kHz reference is desired, set
C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO
output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24
MHz.
Initialization / Application information
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
360 Freescale Semiconductor, Inc.