NXP Semiconductors MKW01Z128, Reference Manual

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UARTx_C5 field descriptions (continued)
Field Description
0 Receiver samples input data using the rising edge of the baud rate clock.
1 Receiver samples input data using the rising and falling edge of the baud rate clock.
0
RESYNCDIS
Resynchronization Disable
When set, disables the resynchronization of the received data word when a data one followed by data
zero transition is detected. This bit should only be changed when the receiver is disabled.
0 Resynchronization during received data word is supported
1 Resynchronization during received data word is disabled
32.3 Functional description
The UART supports full-duplex, asynchronous, NRZ serial communication and
comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate
generator. The following describes each of the blocks of the UART.
32.3.1 Baud rate generation
A 13-bit modulus counter in the baud rate generator derive the baud rate for both the
receiver and the transmitter.
The value from 1 to 8191 written to SBR[12:0] determines the baud clock divisor for the
asynchronous UART baud clock. The SBR bits are in the UART baud rate registers,
BDH and BDL. The baud rate clock drives the receiver, while the transmitter is driven by
the baud rate clock divided by the over sampling ratio. Depending on the over sampling
ratio, the receiver has an acquisition rate of 4 to 32 samples per bit time.
Rx Sampling Clock
[(OSR+1) × Baud Rate]
Baud Rate =
Modulo Divide By
(1 through 8191)
UART ASYNCH
Module Clock
UART ASYNCH Module Clock
Divide By
(OSR+1)
OSR
SBR[12:0]
Baud Rate Generator
Off If [SBR12:SBR0] =0
SBR[12:0] × (OSR+1)
Tx Baud Rate
Figure 32-3. UART baud rate generation
Baud rate generation is subject to two sources of error:
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
636 Freescale Semiconductor, Inc.