NXP Semiconductors MKW01Z128, Reference Manual

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Table 29-1. Modes of operation
Modes Description
Run The LPTMR operates normally.
Wait
The LPTMR continues to operate normally and
may be configured to exit the low-power mode
by generating an interrupt request.
Stop
The LPTMR continues to operate normally and
may be configured to exit the low-power mode
by generating an interrupt request.
Low-Leakage
The LPTMR continues to operate normally and
may be configured to exit the low-power mode
by generating an interrupt request.
Debug
The LPTMR operates normally in Pulse Counter
mode, but counter does not increment in Time
Counter mode.
29.2 LPTMR signal descriptions
Table 29-2. LPTMR signal descriptions
Signal I/O Description
LPTMR0_ALT n I Pulse Counter Input pin
29.2.1 Detailed signal descriptions
Table 29-3. LPTMR interface—detailed signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Timing Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
29.3 Memory map and register definition
LPTMR signal descriptions
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
554 Freescale Semiconductor, Inc.