NXP Semiconductors MKW01Z128, Reference Manual

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I2Cx_C1 field descriptions (continued)
Field Description
0 Disabled
1 Enabled
5
MST
Master Mode Select
When MST is changed from 0 to 1, a START signal is generated on the bus and master mode is selected.
When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from
master to slave.
0 Slave mode
1 Master mode
4
TX
Transmit Mode Select
Selects the direction of master and slave transfers. In master mode this bit must be set according to the
type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave
this bit must be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
3
TXAK
Transmit Acknowledge Enable
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave
receivers. The value of SMB[FACK] affects NACK/ACK generation.
NOTE: SCL is held low until TXAK is written.
0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the
current receiving byte (if FACK is set).
1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or
the current receiving data byte (if FACK is set).
2
RSTA
Repeat START
Writing 1 to this bit generates a repeated START condition provided it is the current master. This bit will
always be read as 0. Attempting a repeat at the wrong time results in loss of arbitration.
1
WUEN
Wakeup Enable
The I2C module can wake the MCU from low power mode with no peripheral bus running when slave
address matching occurs.
0 Normal operation. No interrupt generated when address matching in low power mode.
1 Enables the wakeup function in low power mode.
0
DMAEN
DMA Enable
Enables or disables the DMA function.
0 All DMA signalling disabled.
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request:
• a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic)
• the first byte received matches the A1 register or is a general call address.
Table continues on the next page...
Chapter 36 Inter-Integrated Circuit (I2C)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 719