NXP Semiconductors MKW01Z128, Reference Manual

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8.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: 4004_7000h base + 1040h offset = 4004_8040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DMA
0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
SIM_SCGC7 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DMA
DMA Clock Gate Control
Controls the clock gate to the DMA module.
0 Clock disabled
1 Clock enabled
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
8.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)
NOTE
The CLKDIV1 register cannot be written to when the device is
in VLPR mode.
NOTE
Reset value loaded during System Reset from
FTFA_FOPT[LPBOOT] (See
Table 1 ).
Address: 4004_7000h base + 1044h offset = 4004_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
OUTDIV1
0
OUTDIV4
0
W
Reset
* * * * 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
OUTDIV1 field: The reset value depends on the FTFA_FOPT[LPBOOT]. It is loaded with 0000 (divide by 1), 0001 (divide by
2), 0011 (divide by 4, or 0111 (divide by 8).
•
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
166 Freescale Semiconductor, Inc.