NXP Semiconductors MKW01Z128, Reference Manual

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SIM_CLKDIV1 field descriptions
Field Description
31–28
OUTDIV1
Clock 1 Output Divider value
Sets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of reset, it is
loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight)
depending on the setting of the FTFA_FOPT[LPBOOT] (See
Table 1 ).
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
27–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
OUTDIV4
Clock 4 Output Divider value
Sets the divide value for the bus and flash clock and is in addition to the System clock divide ratio. At the
end of reset, it is loaded with 0001 (divide by 2).
000 Divide-by-1.
001 Divide-by-2.
010 Divide-by-3.
011 Divide-by-4.
100 Divide-by-5.
101 Divide-by-6.
110 Divide-by-7.
111 Divide-by-8.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 8 System Integration Module (SIM)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 167