NXP Semiconductors MKW01Z128, Reference Manual

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Table 9-2. Power mode transition triggers (continued)
Transition # From To Trigger conditions
10 RUN LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011,
STOPCTRL[LLSM]=x (LLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in ARM core.
LLSx RUN Wakeup from enabled LLWU input source or
RESET pin.
11 VLPR LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or
sleep-on-exit modes entered with SLEEPDEEP set, which is
controlled in System Control Register in ARM core.
1. If debug is enabled, the core clock remains to support debug.
2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP
3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If
PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS
9.4.2 Power mode entry/exit sequencing
When entering or exiting low-power modes, the system must conform to an orderly
sequence to manage transitions safely.
The SMC manages the system's entry into and exit from all power modes. This diagram
illustrates the connections of the SMC with other system components in the chip that are
necessary to sequence the system through all power modes.
Chapter 9 System Mode Controller (SMC)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 185