NXP Semiconductors MKW01Z128, Reference Manual

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UARTx_S1 field descriptions (continued)
Field Description
To clear IDLE, read UART_S1 with IDLE set and then read the UART data register (UART_D). After IDLE
has been cleared, it cannot become set again until after a new character has been received and RDRF
has been set. IDLE is set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag
OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but
the previously received character has not been read from UART_D yet. In this case, the new character,
and all associated error information, is lost because there is no room to move it into UART_D. To clear
OR, read UART_S1 with OR set and then read the UART data register (UART_D).
0 No overrun.
1 Receive overrun (new UART data lost).
2
NF
Noise Flag
The advanced sampling technique used in the receiver takes seven samples during the start bit and three
samples in each data bit and the stop bits. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To
clear NF, read UART_S1 and then read the UART data register (UART_D).
0 No noise detected.
1 Noise detected in the received character in UART_D.
1
FE
Framing Error Flag
FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bits were
expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
UART_S1 with FE set and then read the UART data register (UART_D).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
PF
Parity Error Flag
PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received
character does not agree with the expected parity value. To clear PF, read UART_S1 and then read the
UART data register (UART_D).
0 No parity error.
1 Parity error.
33.3.6 UART Status Register 2 (UARTx_S2)
This register contains one read-only status flag.
When using an internal oscillator in a LIN system, it is necessary to raise the break
detection threshold one bit time. Under the worst case timing conditions allowed in LIN,
it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave
running 14% faster than the master. This would trigger normal break detection circuitry
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 655