NXP Semiconductors MKW01Z128, Reference Manual

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1.3.1.3 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.
1.3.1.4 Debug facilities
This device supports standard ARM 2-pin SWD debug port.
1.3.1.5 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
1.3.2 Nested vectored interrupt controller (NVIC) configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at
arm.com .
Nested Vectored
Interrupt Controller
(NVIC)
ARM C
or
te
x-M0+
cor
e
Interrupts
Module
Module
Module
PPB
Figure 1-2. NVIC configuration
Table 1-5. Reference links to related information
Topic Related module Reference
Full description Nested vectored
interrupt controller
(NVIC)
ARM Cortex-M0+ Technical Reference Manual
System memory map — System memory map
Clocking — Clock distribution
Table continues on the next page...
Core modules
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
34 Freescale Semiconductor, Inc.