NXP Semiconductors MKW01Z128, Reference Manual

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Transceiver Digital Control and Communications
MKW01xxRM Reference Manual, Rev. 3, 04/2016
7-2 Freescale Semiconductor, Inc.
• Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The
packet is automatically built with preamble, Sync word, and optional AES, CRC, and DC-free
encoding schemes The reverse operation is performed in reception. The MCU processing overhead
is hence significantly reduced compared to Continuous mode. Depending on the optional features
activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or
unlimited.
Each of these data operation modes is described fully in the following sections.
7.2 Control Block Description
7.2.1 SPI Interface
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol
corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is
implemented.
Three access modes to the registers are provided:
• SINGLE access: an address byte followed by a data byte is sent for a write access whereas an
address byte is sent and a read byte is received for the read access. The NSS pin goes low at the
begin of the frame and goes high after the data byte.
• BURST access: the address byte is followed by several data bytes. The address is automatically
incremented internally between each data byte. This mode is available for both read and write
accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It
goes high only after the last byte transfer.
• FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte
will address the FIFO. The address is not automatically incremented but is memorized and does
not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame
and stay low between each byte. It goes high only after the last byte transfer.
Figure below shows a typical SPI single access to a register.
Figure 7-2. SPI Timing Diagram (single access)
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI
interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is made of: