NXP Semiconductors MKW01Z128, Reference Manual

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UARTx_S2 field descriptions (continued)
Field Description
1
LBKDE
LIN Break Detection Enable
LBKDE enables the break detection. While LBKDE is set, S1[FE] and S1[RDRF] flags are prevented from
setting.
0 Break detection is disabled.
1 Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0,
BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] =
1, BDH[SBNS] = 1)).
0
RAF
Receiver Active Flag
RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared
automatically when the receiver detects an idle line. This status flag can be used to check whether an
UART character is being received before instructing the MCU to go to stop mode.
0 UART receiver idle waiting for a start bit.
1 UART receiver active (RxD input not idle).
33.3.7 UART Control Register 3 (UARTx_C3)
Address: Base a 6h offset
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset 0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8
Ninth Data Bit for Receiver
When the UART is configured for 9-bit data (C1[M] = 1), R8 can be thought of as a ninth receive data bit to
the left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before
reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow
R8 and UART_D to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter
When the UART is configured for 9-bit data (C1[M] = 1), T8 may be thought of as a ninth transmit data bit
to the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is
transferred to the UART shift register after UART_D is written so T8 should be written, if it needs to
change from its previous value, before UART_D is written. If T8 does not need to change in the new value,
such as when it is used to generate mark or space parity, it need not be written each time UART_D is
written.
5
TXDIR
TxD Pin Direction in Single-Wire Mode
When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this field
determines the direction of data at the TxD pin.
Table continues on the next page...
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 657