NXP Semiconductors MKW01Z128, Reference Manual

Page: 813 / 884

FGPIO memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F800_0108 Port Clear Output Register (FGPIOE_PCOR) 32
W
(always
reads 0)
0000_0000h 34.3.3/683
F800_010C Port Toggle Output Register (FGPIOE_PTOR) 32
W
(always
reads 0)
0000_0000h 34.3.4/683
F800_0110 Port Data Input Register (FGPIOE_PDIR) 32 R 0000_0000h 34.3.5/684
F800_0114 Port Data Direction Register (FGPIOE_PDDR) 32 R/W 0000_0000h 34.3.6/684
34.3.1 Port Data Output Register (FGPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output
pins.
Address: Base a 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDO
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PDOR field descriptions
Field Description
PDO Port Data Output
Unimplemented pins for a particular device read as zero.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
34.3.2 Port Set Output Register (FGPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: Base a 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTSO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIO memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
682 Freescale Semiconductor, Inc.