NXP Semiconductors MKW01Z128, Reference Manual

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20.4.4 External Reference Clock
The MCG module can support an external reference clock in all modes. See the device
datasheet for external reference frequency range. When C1[IREFS] is set, the external
reference clock will not be used by the FLL or PLL. In these modes, the frequency can be
equal to the maximum frequency the chip-level timing specifications will support.
If any of the CME bits are asserted the slow internal reference clock is enabled along
with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock
is detected if the OSC0 external reference falls below a minimum frequency (f
loc_high
or
f
loc_low
depending on C2[RANGE0]).
NOTE
All clock monitors must be disabled before entering these low-
power modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx.
On detecting a loss-of-clock event, the MCU generates a system reset if the respective
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG
generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the
PLL LOCK status bit is cleared.
20.4.5 MCG Fixed Frequency Clock
The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock
source for other on-chip peripherals; see the block diagram. This clock is driven by either
the slow clock from the internal reference clock generator or the external reference clock
from the Crystal Oscillator, divided by the FLL reference clock divider. The source of
MCGFFCLK is selected by C1[IREFS].
This clock is synchronized to the peripheral bus clock and is valid only when its
frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is
disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI
mode. This clock is also disabled in Stop mode. The FLL reference clock must be set
within the valid frequency range for the MCGFFCLK.
20.4.6 MCG PLL clock
The MCG PLL Clock (MCGPLLCLK) is available depending on the device's
configuration of the MCG module. For more details, see the clock distribution chapter of
this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is
enabled and S[LOCK0] is set.
Chapter 20 Multipurpose Clock Generator (MCG)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 357