NXP Semiconductors MKW01Z128, Reference Manual

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the DMA transactions are done. When this indication is received, the flag bit and the
associated DMA request are cleared. If the DMA operation failed to remove the situation
that caused the DMA request another request will be issued.
33.4.7 Additional UART functions
The following sections describe additional UART functions.
33.4.7.1 8- and 9-bit data modes
The UART system, transmitter and receiver, can be configured to operate in 9-bit data
mode by setting UART_C1[M]. In 9-bit mode, there is a ninth data bit to the left of the
most significant bit of the UART data register. For the transmit data buffer, this bit is
stored in T8 in UART_C3. For the receiver, the ninth bit is held in UART_C3[R8].
For coherent writes to the transmit data buffer, write to UART_C3[T8] before writing to
UART_D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the
previous character, it is not necessary to write to UART_C3[T8] again. When data is
transferred from the transmit data buffer to the transmit shifter, the value in
UART_C3[T8] is copied at the same time data is transferred from UART_D to the
shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity
in the ninth bit, or it is used with address-mark wake-up so the ninth data bit can serve as
the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled
marker.
33.4.7.2 Stop mode operation
During all stop modes, clocks to the UART module are halted.
No UART module registers are affected in Stop3 mode.
The receive input active edge detect circuit remains active in Stop3 mode. An active edge
on the receive input brings the CPU out of stop and VLPS mode if the interrupt is not
masked (UART_BDH[RXEDGIE] = 1).
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
670 Freescale Semiconductor, Inc.