NXP Semiconductors MKW01Z128, Reference Manual

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LPTMRx_PSR[PCS]
LPTMRx prescaler/glitch
filter clock
MCGIRCLK
OSCERCLK
ERCLK32K
LPO
SIM_SOPT1[OSC32KSEL]
OSC32KCLK
RTC_CLKIN
LPO
Figure 3-4. LPTMRx prescaler/glitch filter clock generation
3.7.5 TPM clocking
The counter for the TPM modules has a selectable clock as shown in the following figure.
NOTE
The chosen clock must remain enabled if the TPMx is to
continue operating in all required low-power modes.
SIM_SOPT2[TPMSRC]
TPM clock
MCGIRCLK
OSCERCLK
MCGPLLCLK ÷2
SIM_SOPT2[PLLFLLSEL]
MCGFLLCLK
Figure 3-5. TPM clock generation
3.7.6 SPI clocking
SPI0 is clocked from the bus clock. That is, the SPI0 module clock is connected to the
chip-level bus clock.
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the
chip-level system clock. SPI1 is therefore disabled in "Partial Stop Mode".
Module clocks
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
100 Freescale Semiconductor, Inc.