NXP Semiconductors MKW01Z128, Reference Manual, Page: 637 / 884

DACx_DATnH field descriptions (continued)
Field Description
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
26.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset,
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only
when the data buffer status is changed.
NOTE
Do not use 32/16-bit accesses to this register.
Address: 4003_F000h base + 20h offset = 4003_F020h
Bit 7 6 5 4 3 2 1 0
Read 0 0 DACBFRPT
F
DACBFRPB
F
Write
Reset
0 0 0 0 0 0 1 0
DACx_SR field descriptions
Field Description
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DACBFRPTF
DAC Buffer Read Pointer Top Position Flag
0 The DAC buffer read pointer is not zero.
1 The DAC buffer read pointer is zero.
0
DACBFRPBF
DAC Buffer Read Pointer Bottom Position Flag
0 The DAC buffer read pointer is not equal to C2[DACBFUP].
1 The DAC buffer read pointer is equal to C2[DACBFUP].
Memory map/register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
506 Freescale Semiconductor, Inc.