NXP Semiconductors MKW01Z128, Reference Manual

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SPIx_C3 field descriptions (continued)
Field Description
4
RNFULLF_
MARK
Receive FIFO nearly full watermark
This bit selects the mark after which the RNFULLF flag is asserted.
0 RNFULLF is set when the receive FIFO has 48 bits or more
1 RNFULLF is set when the receive FIFO has 32 bits or more
3
INTCLR
Interrupt clearing mechanism select
This bit selects the mechanism by which the SPRF, SPTEF, TNEAREF, and RNFULLF interrupts are
cleared.
0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the
FIFOs
1 These interrupts are cleared by writing the corresponding bits in the CI register
2
TNEARIEN
Transmit FIFO nearly empty interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the TNEAREF flag is set. This bit is ignored
and has no function if the FIFOMODE bit is 0.
0 No interrupt upon TNEAREF being set
1 Enable interrupts upon TNEAREF being set
1
RNFULLIEN
Receive FIFO nearly full interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the RNFULLF flag is set. This bit is ignored
and has no function if the FIFOMODE bit is 0.
0 No interrupt upon RNFULLF being set
1 Enable interrupts upon RNFULLF being set
0
FIFOMODE
FIFO mode enable
This bit enables the SPI to use a 64-bit FIFO (8 bytes or four 16-bit words) for both transmit and receive
buffers.
0 FIFO mode disabled
1 FIFO mode enabled
31.4 Functional description
This section provides the functional description of the module.
31.4.1 General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.
While C1[SPE] is set, the four associated SPI port pins are dedicated to the SPI function
as:
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
596 Freescale Semiconductor, Inc.