Interface Overview
3-4
ADSP-BF59x Blackfin Processor Hardware Reference
Peripheral Access Bus (PAB)
The processor has a dedicated low latency peripheral bus that keeps core
stalls to a minimum and allows for manageable interrupt latencies to
time-critical peripherals. All peripheral resources accessed through the
PAB are mapped into the system MMR space of the processor memory
map. The core accesses system MMR space through the PAB bus.
Figure 3-2. Core Block Diagram
INT
RESET
VECTOR
ACK
CORE TIMER
CORE
EVENT
CONTROLLER
DEBUG AND JTAG INTERFACE
JTAG
DSP ID
(8 BITS)
SYSTEM CLOCK
AND POWER
MANAGEMENT
POWER AND
CLOCK
CONTROLLER
PERFORMANCE
MONITOR
MEMORY
MANAGEMENT
UNIT
L1 DATA
L1 INSTRUCTION
LD0
LD1
SD
DA0
DA1
IAB
IDB
CORE
EAB
PROCESSOR
DMA CORE BUS
(DCB)
PAB
32
32
32
32
32
32
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Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...