Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 79 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 3-5
Chip Bus Hierarchy
The core processor has byte addressability, but the programming model is
restricted to only 32-bit (aligned) access to the system MMRs. Byte
accesses to this region are not supported.
PAB Arbitration
The core is the only master on this bus. No arbitration is necessary.
PAB Agents (Masters, Slaves)
The processor core can master bus operations on the PAB. All peripherals
have a peripheral bus slave interface which allows the core to access con-
trol and status state. These registers are mapped into the system MMR
space of the memory map. Appendix B lists system MMR addresses.
The slaves on the PAB bus are:
• System event controller
• Clock and power management controller
• Watchdog timer
• Timer 0–2
• SPORT0–1
• SPI0–1
• General-purpose ports
• UART
• PPI
• TWI
• DMA controller