Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 189 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-89
Direct Memory Access
The
DAB_TRAFFIC_COUNT
field shows the current cycle count remaining in
the DAB traffic period. It initializes to
DAB_TRAFFIC_PERIOD
whenever
DMA_TC_PER
is written, or whenever the DAB bus changes direction or
becomes idle. It then counts down from
DAB_TRAFFIC_PERIOD
to 0 on each
system clock (except for DMA stalls). While this count is nonzero, same
direction DAB accesses are treated preferentially. When this count decre-
ments from 1 to 0, the opposite direction DAB access is treated
preferentially, which may result in a direction change. When this count is
0 and a DAB bus access occurs, the count is reloaded from
DAB_TRAFFIC_PERIOD
to begin a new burst.
The
DEB_TRAFFIC_COUNT
field shows the current cycle count remaining in
the DEB traffic period. It initializes to
DEB_TRAFFIC_PERIOD
whenever
DMA_TC_PER
is written or whenever the DEB bus changes direction or
becomes idle. It then counts down from
DEB_TRAFFIC_PERIOD
to 0 on each
system clock (except for DMA stalls). While this count is nonzero, same
direction DEB accesses are treated preferentially. When this count decre-
ments from 1 to 0, the opposite direction DEB access is treated
preferentially, which may result in a direction change. When this count is
0 and a DEB bus access occurs, the count is reloaded from
DEB_TRAFFIC_PERIOD
to begin a new burst.
Figure 5-26. DMA Traffic Control Counter Register
RO
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Current transfer count remaining in
the MDMA round-robin period
DMA Traffic Control Counter Register (DMA_TC_CNT)
DAB_TRAFFIC_COUNT[2:0]
Current cycle count remaining in the
DAB traffic period
MDMA_ROUND_ROBIN_COUNT[4:0]
DCB_TRAFFIC_COUNT[ 3 :0]
DEB_TRAFFIC_COUNT[ 3 :0]
Reset = 0x0000
Current cycle count remaining
in the DCB traffic period
Current cycle count remaining
in the DEB traffic period