Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 222 / 772

PLL and VR Registers
6-18 ADSP-BF59x Blackfin Processor Hardware Reference

When the core is powered down, V
DDINT
is set to 0 V, and the
internal state of the processor is not maintained, with the exception
of the
VR_CTL
register. Therefore, any critical information stored
internally (memory contents, register contents, and so on) must be
written to a non-volatile storage device prior to removing power.
Powering down V
DDINT
does not affect V
DDEXT
. While V
DDEXT
is still
applied to the processor, external pins are maintained at a three-state level
unless specified otherwise.
To signal the external regulator to power down V
DDINT
:
1. Write 0 to the appropriate bits in the
SIC_IWRx
registers to prevent
enabled peripheral resources from interrupting the hibernate
process.
2. Call the
bfrom_SysControl()
routine; ensure that the
HIBERNATEB
bit in the
VR_CTL
register is set to 0, and the appropriate wakeup
enable bit or bits (
WAKE_EN0
,
WAKE_EN1
,
WAKE_EN2
, or
WAKE_EN3
) are
set to 1.
3. The
bfrom_SysControl()
routine executes until V
DDINT
transi-
tions to 0 V. The
bfrom_SysControl()
routine never returns.
4. When the processor is woken up, the PLL relocks and the boot
sequence defined by the
BMODE[2:0]
pin settings takes effect.
The
WURESET
bit in the
SYSCTRL
register is set and stays set until the next
hardware reset. The
WURESET
bit may control a conditional boot process.
PLL and VR Registers
The user interface to the PLL and VR registers is through the system con-
trol ROM function (
bfrom_SysControl()
) described in “System Control
ROM Function” on page 6-22 . The memory-mapped registers (MMRs)
are shown in Table 6-7 and illustrated in Figure 6-3 through Figure 6-7 .