Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 472 / 772

Functional Description
13-18 ADSP-BF59x Blackfin Processor Hardware Reference
If the transmit buffer remains empty or the receive buffer remains full, the
device operates according to the states of the
SZ
and
GM
bits in
SPI_CTL
.
If
SZ
= 1 and the transmit buffer is empty, the device repeatedly transmits
zeros on the
MOSI
pin. One word is transmitted for each new transfer initi-
ate command. If
SZ
= 0 and the transmit buffer is empty, the device
repeatedly transmits the last word it transmitted before the transmit buffer
became empty.
If
GM
= 1 and the receive buffer is full, the device continues to receive new
data from the
MISO
pin, overwriting the older data in the
SPI_RDBR
regis-
ter. If
GM
= 0 and the receive buffer is full, the incoming data is discarded,
and
SPI_RDBR
is not updated.
Transfer Initiation From Master (Transfer Modes)
When a device is enabled as a master, the initiation of a transfer is defined
by the two
TIMOD
bits of
SPI_CTL
. Based on those two bits and the status of
the interface, a new transfer is started upon either a read of the
SPI_RDBR
register or a write to the
SPI_TDBR
register. This is summarized in
Table 13-1 .

If the SPI port is enabled with
TIMOD
= b#01 or
TIMOD
= b#11, the
hardware immediately issues a first interrupt or DMA request.