Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 72 / 772

Processor-Specific MMRs
2-8 ADSP-BF59x Blackfin Processor Hardware Reference
DCPLB_DATAx Registers
The data CPLB data registers (DCPLB_DATAx), shown in Figure 2-6 ,
contain CPLB control bits for the L1 data memory.
Figure 2-6. Data CPLB Data Register
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data CPLB Data Registers (DCPLB_DATAx)
00 - 1K byte page
01 - 4K byte page
10 - 1M byte page
11 - 4M byte page
PAGE_ S IZE1–0
Reset = 0x00000000
CPLB_VALID
0 - Invalid (disabled) CPLB entry
1 - Valid (enabled) CPLB entry
CPLB_U S ER_WR
0 - Write access prohibited
in User Mode (writes generate
protection violation exceptions)
1 - Write access permitted
in User Mode
CPLB_ S UPV_WR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xFFE0 02 3 C
0xFFE0 022 8
0xFFE0 0214
0xFFE0 0200
0 - Write access prohibited
in Supervisor Mode (writes generate
protection violation exceptions)
1 - Write access permitted
in Supervisor Mode
CPLB_LOCK
0 - Unlocked, CPLB entry replaceable
1 - Locked, CPLB entry not replaceable
CPLB_U S ER_RD
0 - Read access prohibited
in User Mode (reads generate
protection violation exceptionss)
1 - Read access permitted
in User Mode