Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 722 / 772

PPI Registers
A-12 ADSP-BF59x Blackfin Processor Hardware Reference
PPI Registers
PPI registers (0xFFC0 1000 – 0xFFC0 10FF) are listed in Table A-12 .
SPI Controller Registers
SPI0 controller registers (0xFFC0 0500 – 0xFFC0 05FF) are listed in
Table A-13 .
SPI1 controller registers (0xFFC0 3400 – 0xFFC0 34FF) are listed in
Table A-14 .
Table A-12. PPI Registers
Memory-Mapped
Address Register Name For individual bits, see this diagram:
0xFFC0 1000 PPI_CONTROL “PPI Control Register (PPI_CONTROL)” on
page 15-25
0xFFC0 1004 PPI_STATUS “PPI Status Register (PPI_STATUS)” on page 15-29
0xFFC0 1008 PPI_COUNT “PPI Transfer Count Register (PPI_COUNT)” on
page 15-32
0xFFC0 100C PPI_DELAY “PPI Delay Count Register (PPI_DELAY)” on
page 15-32
0xFFC0 1010 PPI_FRAME “PPI Lines Per Frame Register (PPI_FRAME)” on
page 15-33
Table A-13. SPI0 Controller Registers
Memory-Mapped
Address Register Name For individual bits, see this diagram:
0xFFC0 0500 SPI0_CTL “SPI Control (SPI_CTL) Register” on page 13-35
0xFFC0 0504 SPI0_FLG “SPI Flag (SPI_FLG) Register” on page 13-37
0xFFC0 0508 SPI0_STAT “SPI Status (SPI_STAT) Register” on page 13-38