Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 550 / 772

SPORT Registers
14-44 ADSP-BF59x Blackfin Processor Hardware Reference
SPORT Registers
The following sections describe the SPORT registers. Table 14-5 provides
an overview of the available control registers.
Table 14-5. SPORT Register Mapping
Register Name Function Notes
SPORT_TCR1 Primary transmit
configuration register Bits [15:1] can only be written if
bit 0 = 0
SPORT_TCR2 Secondary transmit
configuration register
SPORT_TCLKDIV Transmit clock
divider register Ignored if external SPORT clock
mode is selected
SPORT_TFSDIV Transmit frame sync divider register Ignored if external frame sync mode
is selected
SPORT_TX Transmit data register See description of FIFO buffering at
“SPORT Transmit Data
(SPORT_TX) Register” on
page 14-56
SPORT_RCR1 Primary receive
configuration register Bits [15:1] can only be written if
bit 0 = 0
SPORT_RCR2 Secondary receive
configuration register
SPORT_RCLK_DIV Receive clock
divider register
Ignored if external SPORT clock
mode is selected
SPORT_RFSDIV Receive frame sync
divider register Ignored if external frame sync mode
is selected
SPORT_RX Receive data register See description of FIFO buffering at
“SPORT Receive Data
(SPORT_RX) Register” on
page 14-58
SPORT_STAT Receive and transmit status
SPORT_MCM1 Primary multichannel mode
configuration register Configure this register before
enabling the SPORT