Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual

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Interface Overview
3-6 ADSP-BF59x Blackfin Processor Hardware Reference
PAB Performance
For the PAB, the primary performance criteria is latency, not throughput.
Transfer latencies for both read and write transfers on the PAB are two
SCLK
cycles.
For example, the core can transfer up to 32 bits per access to the PAB
slaves. With the core clock running at 2x the frequency of the system
clock, the first and subsequent system MMR read or write accesses take
four core clocks (
CCLK
) of latency.
The PAB has a maximum frequency of
SCLK
.
DMA Access Bus (DAB), DMA Core Bus (DCB)
The DAB and DCB buses provide a means for DMA-capable peripherals
to gain access to on-chip memory with little or no degradation in core
bandwidth to memory.
DAB and DCB Arbitration
Thirteen DMA channels and bus masters support the DMA-capable
peripherals in the processor system. The nine peripheral DMA channel
controllers can transfer data between peripherals and internal memory.
Both the read and write channels of the dual-stream memory DMA con-
troller access their descriptor lists through the DAB.
The DCB has priority over the core processor on arbitration into L1
SRAM. The processor has a programmable priority arbitration policy on
the DAB.
Table 3-1 shows the default arbitration priority.
Table 3-1. DAB and DCB Arbitration Priority
DAB, DCB Master Default Arbitration Priority
PPI receive or transmit 0 - highest
SPORT0 receive 1