Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 564 / 772

SPORT Registers
14-58 ADSP-BF59x Blackfin Processor Hardware Reference
SPORT Receive Data (SPORT_RX) Register
The
SPORT_RX
register is a read-only register. Writes produce a peripheral
bus error. The same location is read for both primary and secondary data.
Reading from this register space causes reading of the receive FIFO. This
16-bit FIFO is 8 deep for receive word length
≤
16 and 4 deep for
length > 16 bits. The FIFO is shared by both primary and secondary
receive data. The order for reading using peripheral bus/DMA reads is
important since data is stored in differently depending on the setting of
the
SLEN
and
RXSE
configuration bits.
Data storage and data ordering in the FIFO are shown in Figure 14-31 on
page 14-58 . The
SPORT_RX
register is shown in Figure 14-32 on
page 14-60 .
Figure 14-31. SPORT Receive FIFO Data Ordering
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
W7
0
PRIMARY AND
SECONDARY ENABLED
DATA LENGTH <= 16 BITS
PRIMARY AND
SECONDARY ENABLED
DATA LENGTH > 16 BITS
15
W6
W5
W4
W3
W2
W1
W0
W3 LOW
0 15
W3 HIGH
W2 LOW
W2 HIGH
W1 LOW
W1 HIGH
W0 LOW
W0 HIGH
SECONDARY W3
0 15
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
PRIMARY
SECONDARY
SECONDARY
SECONDARY
W3
W2
W2
W1
W1
W0
W0
SECONDARY W1 LOW
0 15
SECONDARY
SECONDARY
SECONDARY
W1 HIGH
W1 LOW
W1 HIGH
W0 LOW
W0 HIGH
W0 LOW
W0 HIGH
4 WORDS OF
PRIMARY DATA AND
4 WORDS OF
SECONDARY DATA
IN FIFO
2 WORDS OF
PRIMARY DATA AND
2 WORDS OF
SECONDARY DATA
IN FIFO
FROM Rx HOLD REGISTER
TO
PAB/DAB
BUSES TO
PAB/DAB
BUSES
TO
PAB/DAB
BUSES TO
PAB/DAB
BUSES
FROM Rx HOLD REGISTER
FROM Rx HOLD REGISTER
FROM Rx HOLD REGISTER
ONLY PRIMARY ENABLED
DATA LENGTH <= 16 BITS
ONLY PRIMARY ENABLED
DATA LENGTH > 16 BITS
8 WORDS OF
PRIMARY DATA
IN FIFO
4 WORDS OF
PRIMARY DATA
IN FIFO