ADSP-BF59x Blackfin Processor Hardware Reference
13-35
SPI-Compatible Port Controller
SPI Control (SPI_CTL) Register
The
SPI_CTL
register is used to configure and enable the SPI system. This
register is used to enable the SPI interface, select the device as a master or
slave, and determine the data transfer format and word size.
The term “word” refers to a single data transfer of either 8 bits or 16 bits,
depending on the word length (
SIZE
) bit in
SPI_CTL
. There are two special
bits which can also be modified by the hardware:
SPE
and
MSTR
.
The
TIMOD
field is used to specify the action that initiates transfers to/from
the receive/transmit buffers. When set to b#00, a SPI port transaction is
begun when the receive buffer is read. Data from the first read will need to
be discarded since the read is needed to initiate the first SPI port transac-
tion. When set to b#01, the transaction is initiated when the transmit
buffer is written. A value of b#10 selects DMA receive mode and the first
transaction is initiated by enabling the SPI for DMA receive mode. Subse-
quent individual transactions are initiated by a DMA read of the
SPI_RDBR
register. A value of 11 selects DMA transmit mode and the transaction is
initiated by a DMA write of the
SPI_TDBR
register.
The
PSSE
bit is used to enable the
SPISS
input for an external master.
When not used,
SPISS
can be disabled, freeing up a pin for an alternate
function.
The
EMISO
bit enables the
MISO
pin as an output. This is needed in an
environment where the master wishes to transmit to various slaves at one
time (broadcast). Only one slave is allowed to transmit data back to the
master. Except for the slave from whom the master wishes to receive, all
other slaves should have this bit cleared.
The
SPE
and
MSTR
bits can be modified by hardware when the
MODF
bit of
the
SPI_STAT
register is set. See
“Mode Fault Error (MODF)” on
page 13-39
.
Figure 13-13 on page 13-36
provides the bit descriptions for
SPI_CTL
.
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...