Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 532 / 772

Functional Description
14-26 ADSP-BF59x Blackfin Processor Hardware Reference
RFS
pulse (when the frame sync is internally generated). This enables a
frame sync to initiate periodic transfers. The counting of serial clock
cycles applies to either internally or externally generated serial clocks.
The formula for the number of cycles between frame sync pulses is:
# of transmit serial clocks between frame sync assertions =
TFSDIV
+ 1
# of receive serial clocks between frame sync assertions =
RFSDIV
+ 1
Use the following equations to determine the correct value of
TFSDIV
or
RFSDIV
, given the serial clock frequency and desired frame sync frequency:
SPORT TFS frequency = (
TSCLK
frequency)/(
SPORT_TFSDIV
+ 1)
SPORT RFS frequency = (
RSCLK
frequency)/(
SPORT_RFSDIV
+ 1)
The frame sync would thus be continuously active (for transmit if
TFSDIV
= 0 or for receive if
RFSDIV
= 0). However, the value of
TFSDIV
(or
RFSDIV
) should not be less than the serial word length minus 1 (the value
of the
SLEN
field in
SPORT_TCR2
or
SPORT_RCR2
). A smaller value could
cause an external device to abort the current operation or have other
unpredictable results. If a SPORT is not being used, the
TFSDIV
(or
RFSDIV
) divisor can be used as a counter for dividing an external clock or
for generating a periodic pulse or periodic interrupt. The SPORT must be
enabled for this mode of operation to work.
Maximum Clock Rate Restrictions
Externally generated late transmit frame syncs also experience a delay from
arrival to data output, and this can limit the maximum serial clock speed.
See the
ADSP-BF592 Blackfin Processor Data Sheet for exact timing
specifications.