Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 92 / 772

System Interrupt Controller Registers
4-10 ADSP-BF59x Blackfin Processor Hardware Reference
by the system-level interrupt registers (
SIC_IWR
,
SIC_ISR
,
SIC_IMASK
,
SIC_IAR
).
If multiple interrupt sources share a single core interrupt, then the inter-
rupt service routine (ISR) must identify the peripheral that generated the
interrupt. The ISR may then need to interrogate the peripheral to deter-
mine the appropriate action to take.
System Interrupt Controller Registers
The SIC registers are described in the following sections.
These registers can be read from or written to at any time in supervisor
mode. It is advisable, however, to configure them in the reset interrupt
service routine before enabling interrupts. To prevent spurious or lost
interrupt activity, these registers should be written to only when all
peripheral interrupts are disabled.
System Interrupt Assignment (SIC_IAR) Register
The
SIC_IAR
register maps each peripheral interrupt ID to a correspond-
ing IVG priority level. This is accomplished with 4-bit groupings that
translate to IVG levels as shown in
Table 4-2 and Figure 4-2 on
page 4-11 . In other words, Table 4-2 defines the value to write in a 4-bit
field within
SIC_IAR
in order to configure a peripheral interrupt ID for a
particular IVG priority. Refer to Table 4-1 on page 4-3 for information
on SIC_IAR mappings for this specific processor.